September 23, 2008   
Profitable SoC Design: Using Logic NVM to Reduce SOC Costs
 
Pearl Cheng
VP Engineering
Kilopass Technology Inc.
Current trends in the semiconductor industry emphasize the inherent business and engineering risks associated with the development and production of a new chip. With very low incremental costs for implementing personalization design elements into system architectures, designers and technology leaders are now realizing tremendous value.
Methods are discussed here that illustrate the opportunities for reducing costs and maximizing economic value with new trends in system architectures. These system architecture trends are enabled by the availability of high density Logic NVM memory solutions. more >>
Check our portfolio of silicon proven data converter IP for your SoCs more >>
Find out about our diverse IP portfolio, SerDes solutions and more >>
ESD protection cells for DisplayPort - 40nm TSMC from Sarnoff Europe
ESD protection cells for Gigabit Ethernet applications - 40nm TSMC
from Sarnoff Europe
Verification IP for PCI Express 1.1/2.0/3.0 from Denali Software
An end-to-end solution for PCIe-based flash memory systems
from Denali Software
AHB-PCI Express Bridge IP Core
from PLDA
AXI-PCI Express Bridge - Gen I and Gen II Compatible from PLDA
MIPI SLIMbus - Serial Low-power Interchip Media Bus Device...
from Arasan Chip Systems
MIPI CSI - Camera Serial Interface Receiver Controller
from Arasan Chip Systems
CEVA MM2000 - Production-Proven, Programmable Multimedia Solution
High Voltage & ultra Low Leakage Standard cell library
from Dolphin Integration
ultra Low power Consumption standard cell library 65 nm
from Dolphin Integration
WLAN MIMO PHY IP core
from SeaSolve Software
WLAN MIMO MAC IP core
from SeaSolve Software
2-4GHz High-Performance Fractional-N Digital Phase-Locked...
from Cambridge Analog Technologies
Dual I/Q 8-Bit 1-GSPS Pipeline Analog to Digital Converter
from Cambridge Analog Technologies
Fully programmable multimedia platform targeting high-end...
from CEVA
Camera Interface supporting up to 12.6 Megapixel with internal...
from Silicon Image
XPM / OTP - 1K-bit to 128K-bits NVM IP / OTP on TSMC 65 nm G+
from Kilopass Technology
Designs By Node Q2 2008

 
Leading edge node design starts are now getting more traction according to this recent study; however, the majority of designs are still focused on legacy nodes with the bulk centered around 90nm.
PHY / Modems solutions
 
IP for Systems that Work
 
Total IP Solution
SATA, USB, SD/MMC, etc.
 


 


 


 
MIPI D-PHY - Source Synchronous Marco for MIPI DSI, CSI and UniPro
from Arasan Chip Systems
MIPI DSI - Display Serial Interface Device Controller
from Arasan Chip Systems
Designware AMBA 3 AXI Register Slice performs AXI channel...
from Synopsys
CRC32 Generator/Checker for 10Gbps from MorethanIP
DesignWare DDR2/DDR3-Lite Memory Controller implements a...
from Synopsys
MIPI CSI - Camera Serial Interface Transmitter Controller
from Arasan Chip Systems
H.264/MPEG-4 video decoder capable of 1080p at 60 fps....
from Bluespec
TSMC CL013LV 0.13um - 66MHz-330MHz from True Circuits
 
TCI PLLs and DDR DLLs are high quality, low jitter, silicon proven hard macros. They are available in TSMC, UMC, CHRT and Common Platform processes from 180nm to 40nm. Visit the timing experts at www.truecircuits.com.
 
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Freescale to acquire enterprise security sw supplier Intoto
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Algotronix offers the leading AES cryptography solutions for FPGA. Widely adopted in the defense sector, these highly configurable IP cores are supplied as VHDL source code. The AES-GCM solution provides 10Gbit/s performance on minimum size packets on a Virtex 5 FPGA. Our DesignTag product protects semiconductor company revenue by detecting counterfeiting and design piracy. more >>
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